1. Field of Invention
The field of invention relates generally to computer systems and, more specifically but not exclusively, relates to striping data across multiple cache lines to prevent false sharing.
2. Background Information
Computer systems typically include one or more I/O devices. I/O device drivers are used for communicating with I/O devices. Information is received and sent from an I/O device in the form of data blocks. For example, a network interface card (NIC) receives and sends data blocks in the form of packets.
Control information between an I/O device and its corresponding I/O device driver is encapsulated in descriptors. A descriptor points to a buffer in memory that stores a data block. Normally, the descriptors are stored sequentially in a ring buffer in memory.
Usually, the size of a descriptor is smaller than the size of a cache line. More than one descriptor can fit into a single cache line of a computer system. Thus, when a descriptor is loaded from memory into a cache line, other descriptors corresponding to other data blocks may also be loaded into the same cache line.
Multi-processor computer systems also use caching techniques. In a multic-processor system, a situation may occur in which each processor is working in a separate cache, rather than in the shared memory. Changes to a processor's local cache will be communicated to other processors to keep the data coherent. Generally, a cache coherency protocol (also referred to as cache consistency) ensures the data in a cache is accuarte and updated before the processor consumes it. The data in a cache line gets written to memory when a new memory area is loaded to that cache line. This is important for consistent operation of multiprocessor systems in which each CPU has a non-shared cache of a shared memory area.
In a multi-processor system, having multiple descriptors for different data blocks in a single cache line may lead to false sharing. Generally, false sharing occurs when multiple processors want access to information contained in a single cache line. System performance is degraded because a processor must wait for access to the cache line while another processor completes activity with the cache line. In multi-processor systems, a performance bottleneck can arise from unnecessary cache-cache transfers.